1. Field of the Invention
The present invention relates to a technique for fabricating a semiconductor device such as a semiconductor integrated circuit in which a doping process is incorporated, and it relates also to a semiconductor device (element) fabricated by the same technique.
2. Prior Art
Diffusion and ion implantation processes are the conventionally known processes practiced in the art for doping impurities. Diffusion process comprises heating the semiconductor under an atmosphere of high temperature in the range of from 500 to 1,200° C. to allow impurities to diffuse inside the semiconductor. Ion implantation comprises accelerating ionized impurities in an electric field, and bombarding the desired portions of the semiconductor with the thus accelerated ions. However, the ion implantation process causes considerable damage to the crystal structure due to the high energy ions bombarded to the semiconductor, and leaves the semiconductor in an amorphous state or a state similar thereto. Accordingly, the above diffusion process or a thermal treatment equivalent thereto is necessary to recover the crystal from the considerably impaired electrical properties. The ion implantation process is indispensable in fabricating VLSI (very large scale integration) and ULSI (ultra large scale integration), because the impurity concentration can be more easily controlled by this process as compared with the diffusion process.
The ion implantation process, however, is not completely free of problems. The problem to be considered first is how to control the diffusion of the implanted ions. This problem is particularly serious in the so-called quarter-micron devices, in which the design requires a rule of 0.5 μm or less in width. Recently, the formation of a shallow impurity-diffused domain (diffusion region) is further required. However, it is difficult to form a shallow diffusion region of 0.1 μm or less in depth with sufficient reproducibility. The above problems are discussed in further detail below referring to FIG. 2.
The first problem above occurs because the ions implanted into the semiconductor by ion implantation diffuse along the sides due to secondary scattering, and because the ions extend thermally around the bombarded portion during the thermal treatment. These effects were of no problem in the conventional processes in which the design rule (typically the width of a gate contact of a MOSFET) was still in the range of 1.0 μm or more. However, with a rule below 1.0 μm, the diffusion portion which forms due to the above effect then accounts for a larger area as compared with the width of the gate contact. Referring to FIG. 2(A), a gate contact 205 then geometrically overlaps diffusion regions (source and drain) 202 and 203. Such an overlap may form a parasitic capacitance for the gate contact and the source and drain, to result in lowering of the operation speed.
The second problem occurs due to roughly classified two reasons. One is attributed to the thermal diffusion similar to the case pointed in the above first problem. This makes it difficult to reduce the diffusion region to a thickness of 0.1 μm or less. The other is due to the channeling effect which accompanies the ion implantation, and is particularly distinct when a crystalline semiconductor is used. That is, the ions incident vertical to the crystal plane pass without being scattered as to reach a deep portion inside the substrate.
To circumvent the channeling effect, the ion implantation in the conventional processes was performed by taking an incident angle of several degrees with respect to the crystal plane. However, there had been cases in which the orbit of the ions was bent inside the semiconductor to incidentally match with the channeling condition. Then, the ions penetrate deep into the substrate as shown in FIG. 2(B). When ion implantation is performed on a polycrystalline semiconductor, on the other hand, the ions then accommodate themselves at various depth levels because the crystal planes are randomly distributed in a polycrystalline semiconductor.
Furthermore, other problems are encountered when a polycrystalline semiconductor is used. In a polycrystalline semiconductor, the doped impurities tend to undergo thermal diffusion along the grain boundaries between the crystals. Accordingly, as shown in FIG. 2(C), a uniform doping is not feasible for a polycrystalline semiconductor. These problems remains unsolved as long as a conventional process of ion implantation with recrystallization by heat treatment is taken. As a matter of course, a diffusion process is far from being a solution to the problem.
A problem to be solved by the present invention is to prevent impurities from being diffused along the lateral sides. Another problem to be solved by the present invention is to control the diffusion of the impurities within a depth of 0.1 μm, and preferably within 50 nm. An object of the present invention is to provide a solution for either or both of the problems above, using a single crystal or a polycrystalline semiconductor, or any semiconductor material similar thereto. As a result, the present invention enables stable fabrication of a MOS device having a channel length of 1.0 μm or shorter, and typically, such having a channel length in the range of from 0.1 to 0.3 μm.